Careers

Our company's main focus is the design process for implementing ICs according to customer requirement. We commit to providing a friendly working environment, to giving employees respect and esteem, to helping employees balance work and life, and to providing good salaries and benefits. Join us to explore an exciting career at SiNBLE!

Memory Circuit Design Engineer (Experienced)

Location: Ho Chi Minh, Vietnam
Responsibilities
Design, Optimization and Verification of IP Memory Compiler
Design include High-speed, High-density or Low-Power variant
Actively participate in design methodology and QA system improvement
Cooperate with Layout and CAD engineers for optimal schedule
Assist testchip team in silicon verification and provide silicon validation report
Provide mentorship and guidance to junior engineers
Requirements
Solid knowledge on SRAM architecture and design methodology
Solid knowledge on device physics, process variation and SRAM bit cell behavior
Familiar with Performance, Power and Area (PPA) design optimization
Familiar with Timing/Power characterization, Function Verification and other SRAM compiler QA tools setup
BS or MS degree in EE or CS related
Good English communication skills
Experience in FinFET is a plus
Min 3 years working experience
Candidate with lesser experience will be considered for junior position

Memory Layout Design Engineer (Experienced)

Location: Ho Chi Minh, Vietnam
Responsibilities
Cell & block level layout, macro planning and interconnect
Physical verification (LVS, DRC, ERC, EMIR)
Actively participate in layout QA methodology and QA system improvement
Cooperate with designers for optimal Performance, Power and Area (PPA)
Provide mentorship and guidance to junior engineers
Requirements
Familiar with memory layout such as SRAM, ROM or TCAM
Familiar with Floor-planning, P/G mesh planning, signal routing and matching layout
Familiar with Cadence/Synopsys layout editor and physical verification tools
Experience in schedule estimation
BS degree in EE or CS related
Good English communication skills
Experience in FinFET is a plus
Min 3 years working experience
Candidate with lesser experience will be considered for junior position

Memory CAD Engineer (Experienced)

Location: Ho Chi Minh, Vietnam
Responsibilities
Develop and support memory design flow
Design flow automation, such as layout/schematic generation, simulation deck generation and characterization automation
Evaluate EDA tools and integrate into existing CAD flow
Interface with IT and EDA to enhance productivity
Requirements
Familiar with library or memory characterization
Familiar with Synopsys liberty format
Familiar with circuit simulation tools and LPE tools
Familiar with C-shell, TCL, C/C++ or Python
BS or MS degree in EE or CS related
Good English communication skills
Min 3 years working experience
Candidate with lesser experience will be considered for junior position

RTL System Integration Engineer (Experienced)

Location: Ho Chi Minh, Vietnam
Responsibilities
Subsystem Integration (PCIe, DDR, USB)
Integrate controller and PHY at RTL level
Integrate controller and PHY IP level SDC and generate subsystem level SDC
Pass subsystem simulation
Perform Synthesis (RTL to Netlist)
Pass QA items such as LEC, STA, In-house Design Kit
Generate HDM model (subsystem CDC model, for SOC level CDC)
Generate subsystem document & database package
Requirements
Familiar with System Verilog
Familiar with Front-end EDA tools
  • Familiar with PCIe Gen-4 spec
  • Synopsys Design Compiler, PrimeTime, Lint
  • LEC tool, Cadence Conformal or Synopsys Formality
  • Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC
    •
    Familiar with PCIe Gen-4 spec
    Familiar with AMBA AXI, AHB, APB spec
    BS or MS degree in EE or CS related
    Good English communication skills
    Experience in UVM is a plus
    Min 5 years working experience
    Candidate with lesser experience will be considered for junior position

    Functional Verification Engineer (Experienced)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    IP Connectivity, IP Configuration Verification and Bus Protocol Verification at SOC Level
    ASIC Functional Verification of IP Multi-Configuration and Multi-Protocol at SOC Level
    Understand expected functionality of designs, develop corresponding test plans, setup and develop components in Verification environment
    Achieve coverage goals through various methodology such as UVM, Coverage-Driven Verification, Transaction-Level Modeling, System Verilog Interface, Virtual Sequencer etc
    Project Management and provide weekly progress update to Customers
    Requirements
    Familiar with Synopsys Verification tools
    Excellent team and interpersonal skills
    Good English communication skills
    Experience in ARM CPU, PCIe or USB 3.x system verification is a plus
    Min 3 years working experience
    Candidate with lesser experience will be considered for junior position

    SoC Physical Design Engineer (Experienced)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    ASIC physical implementation by using automatic place and route tools
    Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization
    Physical verification signoff including DRC, LVS, ERC, Antenna and ESD
    Coordinate cross-site communication and coordination among internal supporting groups
    Requirements
    Familiar with Cadence Innovus or Synopsys ICC flow
    Familiar with timing closure, IR drop analysis and physical verification
    Excellent team and interpersonal skills
    BS or MS degree in EE or CS related
    Good English communication skills
    Min 3 years working experience
    Candidate with lesser experience will be considered for junior position

    ASIC Consultant Engineer (Experienced)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    Main technical contact window and consultant of ASIC implementation from RTL-in/netlist-in to tapeout
    Perform project management and coordinate among internal supporting groups
    DFT implementation, including MBIST, DFT insertion, JTAG and ATPG generation
    STA signoff
    Advice customers on technical issues related to floorplan, sdc, clock tree, package, power etc
    Requirements
    Familiar with PrimeTime, Debussy, Verilog-XL, Design Compiler and Formal Verification tools
    Excellent team and interpersonal skills
    BS or MS degree in EE or CS related
    Good English communication skills
    Experience in DFT is a plus
    Min 3 years working experience
    Candidate with lesser experience will be considered for junior position

    Standard Cell Library Design Engineer (Experienced)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    Standard cell library development for new process node
    Support customization through PPA optimization on architecture, circuit and design methodology
    Collaborate with multiple foundries and design methodology/flow team
    Requirements
    Solid knowledge in standard cell library design and layout
    Solid knowledge on device physics and process variation
    BS or MS degree in EE or CS related
    Good English communication skills
    Experience in C-shell, TCL, C/C++, Perl or Python is a plus
    Min 3 years working experience
    Candidate with lesser experience will be considered for junior position

    Standard Cell Library CAD Engineer (Entry level)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    Standard cell library characterization, modelling & verification
    Support In-house automation flow creation, enhancement & maintenance
    Support EDA tool evaluation
    Requirements
    Familiar with Spice simulation and CMOS circuit
    Familiar with C-shell, TCL, C/C++, Perl or Python
    Basic understanding of statistical theory and library variation format (LVF)
    BS degree in EE or CS related
    Good English communication skills
    Experience with characterization tool is a plus (eg. Cadence Liberate or Synopsys SiliconSmart)
    Fresher is welcome to apply

    Standard Cell Library Layout Engineer (Experienced)

    Location: Ho Chi Minh, Vietnam
    Responsibilities
    Standard Cell Library Custom Layout and Optimization
    Collaborate with designers to achieve Best-In-Class Performance, Power and Area
    Physical verification (LVS, DRC, ERC, Antenna)
    Requirements
    Familiar with Standard Cell IP Custom Layout
    BS degree in EE or CS related
    Basic understanding of statistical theory and library variation format (LVF)
    Experience in FinFET is a plus
    Min 3 years working experience
    Candidate with lesser experience will be considered for junior position